参考代码

components/system/include/drivers/chip/_hal.h

@@ -0,0 +1,103 @@
+#ifndef ___HAL_H__
+#define ___HAL_H__
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+typedef uint8_t hal_id_t;
+
+#ifdef __cplusplus
+}
+#endif
+
+#include "drivers/chip/gpio.h"
+#include "drivers/chip/clk.h"
+#include "drivers/chip/irq.h"
+#include "drivers/chip/uart.h"
+#include "drivers/chip/i2c.h"
+#include "drivers/chip/spi.h"
+#include "drivers/chip/phy.h"
+#include "drivers/chip/adc.h"
+#include "drivers/chip/cmp.h"
+#include "drivers/chip/dac.h"
+#include "drivers/chip/dma.h"
+#include "drivers/chip/tim.h"
+#include "drivers/chip/tick.h"
+#include "drivers/chip/fmc.h"
+#include "drivers/chip/wdt.h"
+#include "drivers/chip/lpm.h"
+#include "drivers/chip/misc.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+typedef struct
+{
+    uint8_t pin;
+    gpio_dir_t dir;
+    gpio_pud_t pull;
+} hal_pin_hdl_t;
+
+typedef struct
+{
+    hal_pin_hdl_t pin_txd;
+    hal_pin_hdl_t pin_rxd;
+    hal_id_t id;
+    uint8_t irq_prior;
+    uint32_t br;
+} hal_uart_hdl_t;
+
+typedef struct
+{
+    hal_pin_hdl_t pin_sck;
+    hal_pin_hdl_t pin_sda;
+    hal_id_t id;
+    uint8_t irq_prior;
+    uint32_t freq;
+} hal_i2c_hdl_t;
+
+typedef struct
+{
+    hal_pin_hdl_t pin_sck;
+    hal_pin_hdl_t pin_mosi;
+    hal_pin_hdl_t pin_miso;
+    hal_id_t id;
+    spi_mode_t mode;
+    uint8_t irq_prior;
+    uint32_t freq;
+} hal_spi_hdl_t;
+
+typedef struct
+{
+    hal_id_t id;
+    uint16_t vref_mv;
+    uint32_t value_max;
+    uint32_t channel_mask;
+} hal_adc_hdl_t;
+
+void drv_hal_init(void);
+void drv_hal_deinit(void);
+
+int drv_hal_gpio_pin_init(const hal_pin_hdl_t *gpio_hdl);
+int drv_hal_uart_init(const hal_uart_hdl_t *uart_hdl);
+int drv_hal_i2c_init(const hal_i2c_hdl_t *i2c_hdl);
+int drv_hal_spi_init(const hal_spi_hdl_t *spi_hdl);
+int drv_hal_drv_adc_init(const hal_adc_hdl_t *adc_hdl);
+
+void drv_hal_debug_enable(void);
+void drv_hal_debug_disable(void);
+
+void drv_hal_sys_reset(void);
+void drv_hal_sys_exit(int status);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

components/system/include/drivers/chip/adc.h

@@ -0,0 +1,40 @@
+#ifndef __ADC_H__
+#define __ADC_H__
+
+#include "drivers/chip/_hal.h"
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+typedef void (*adc_isr_cb_fn)(uint8_t channel_id);
+
+void drv_adc_pin_configure(hal_id_t id, uint8_t pin);
+
+void drv_adc_enable(hal_id_t id);
+void drv_adc_disable(hal_id_t id);
+
+void drv_adc_init(hal_id_t id, unsigned channel_mask, uint32_t sampling_length);
+void drv_adc_deinit(hal_id_t id, unsigned channel_mask);
+
+int drv_adc_irq_callback_enable(hal_id_t id, uint8_t channel_id, adc_isr_cb_fn cb);
+int drv_adc_irq_callback_disable(hal_id_t id, uint8_t channel_id);
+
+void drv_adc_irq_enable(hal_id_t id, int priority);
+void drv_adc_irq_disable(hal_id_t id);
+
+void drv_adc_start(hal_id_t id, unsigned channel_mask);
+void drv_adc_stop(hal_id_t id, unsigned channel_mask);
+
+bool drv_adc_is_busy(hal_id_t id, uint8_t channel_id);
+bool drv_adc_is_ready(hal_id_t id, uint8_t channel_id);
+
+int drv_adc_read(hal_id_t id, uint8_t channel_id);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

components/system/include/drivers/chip/clk.h

@@ -0,0 +1,17 @@
+#ifndef __CLK_H__
+#define __CLK_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+unsigned drv_clk_get_cpu_clk(void);
+
+int drv_clk_calibration(unsigned tar_clk, unsigned cur_clk);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

components/system/include/drivers/chip/cmp.h

@@ -0,0 +1,57 @@
+#ifndef __HAL_CMP_H__
+#define __HAL_CMP_H__
+
+#include "drivers/chip/_hal.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+typedef void (*cmp_isr_cb_fn)(void);
+
+typedef enum __packed
+{
+    _CMP_OUTPUT_NONE, // 没有任何输出动作
+    _CMP_OUTPUT_IO,   // 输出到 IO
+    _CMP_OUTPUT_EXTI, // 触发 中断线
+    _CMP_OUTPUT_TIM,  // 触发 定时器的输入
+} cmp_output_t;
+
+typedef enum __packed
+{
+    _CMP_INT_EDGE_NONE,
+    _CMP_INT_EDGE_FALL,
+    _CMP_INT_EDGE_RISE,
+    _CMP_INT_EDGE_BOTH,
+} cmp_int_edge_t;
+
+void drv_cmp_pin_configure_in(hal_id_t id, uint8_t pin);
+void drv_cmp_pin_configure_out(hal_id_t id, uint8_t pin);
+
+void drv_cmp_enable(hal_id_t id);
+void drv_cmp_disable(hal_id_t id);
+
+void drv_cmp_init(hal_id_t id, cmp_output_t output);
+void drv_cmp_deinit(hal_id_t id);
+
+int drv_cmp_get_out_value(hal_id_t id);
+
+int drv_cmp_irq_callback_enable(hal_id_t id, cmp_isr_cb_fn cb);
+int drv_cmp_irq_callback_disable(hal_id_t id);
+
+void drv_cmp_irq_enable(hal_id_t id, cmp_int_edge_t edge, int priority);
+void drv_cmp_irq_disable(hal_id_t id);
+
+void drv_cmp_start(hal_id_t id);
+void drv_cmp_stop(hal_id_t id);
+
+void drv_cmp_set_cmp_value(hal_id_t id, uint16_t value);
+
+uint8_t drv_cmp_read(hal_id_t id);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

components/system/include/drivers/chip/dac.h

@@ -0,0 +1,33 @@
+#ifndef __DAC_H__
+#define __DAC_H__
+
+#include "drivers/chip/_hal.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+typedef void (*dac_isr_cb_fn)(void);
+
+void drv_dac_pin_configure(hal_id_t id, uint8_t pin);
+
+void drv_dac_enable(hal_id_t id);
+void drv_dac_disable(hal_id_t id);
+
+int drv_dac_init(hal_id_t id, unsigned channel_mask, unsigned bit_width);
+int drv_dac_deinit(hal_id_t id, unsigned channel_mask);
+
+int drv_dac_irq_callback_enable(hal_id_t id, dac_isr_cb_fn cb);
+int drv_dac_irq_callback_disable(hal_id_t id);
+
+void drv_dac_irq_enable(hal_id_t id, int priority);
+void drv_dac_irq_disable(hal_id_t id);
+
+void drv_dac_write(hal_id_t id, unsigned channel_id, int value);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

components/system/include/drivers/chip/dma.h

@@ -0,0 +1,42 @@
+#ifndef __DMA_H__
+#define __DMA_H__
+
+#include "drivers/chip/_hal.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+typedef enum __packed
+{
+    _DMA_DIR_MEM_TO_MEM,
+    _DMA_DIR_PER_TO_MEM,
+    _DMA_DIR_MEM_TO_PER,
+} dma_dir_t;
+
+typedef void (*dma_isr_cb_fn)(void);
+
+void drv_dma_enable(hal_id_t id);
+void drv_dma_disable(hal_id_t id);
+
+int drv_dma_init(hal_id_t id, unsigned channel, unsigned prio_level);
+int drv_dma_deinit(hal_id_t id, unsigned channel);
+
+int drv_dma_irq_callback_enable(hal_id_t id, unsigned channel, dma_isr_cb_fn cb);
+int drv_dma_irq_callback_disable(hal_id_t id, unsigned channel);
+
+void drv_dma_irq_enable(hal_id_t id, unsigned channel, int priority);
+void drv_dma_irq_disable(hal_id_t id, unsigned channel);
+
+void drv_dma_set(hal_id_t id, unsigned channel, void *dest, unsigned dest_bit_width, bool dest_inc_mode, const void *src, unsigned src_bit_width, bool src_inc_mode, unsigned count, dma_dir_t dir);
+void drv_dma_start(hal_id_t id, unsigned channel);
+void drv_dma_stop(hal_id_t id, unsigned channel);
+
+unsigned drv_dma_get_remain(hal_id_t id, unsigned channel);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

components/system/include/drivers/chip/fmc.h

@@ -0,0 +1,40 @@
+#ifndef __FMC_H__
+#define __FMC_H__
+
+#include <stdbool.h>
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+void drv_fmc_enable(void);
+void drv_fmc_disable(void);
+
+void drv_fmc_lock(void);
+void drv_fmc_unlock(void);
+
+unsigned drv_fmc_get_rom_base(void);
+unsigned drv_fmc_get_rom_size(void);
+unsigned drv_fmc_get_sector_base(unsigned addr);
+unsigned drv_fmc_get_sector_size(unsigned addr);
+
+int drv_fmc_sector_erase(unsigned addr);
+int drv_fmc_data_write(unsigned addr, const void *src, unsigned size);
+int drv_fmc_data_read(void *dest, unsigned addr, unsigned size);
+
+bool drv_fmc_is_busy(void);
+
+int drv_fmc_set_read_protection(bool enable);
+int drv_fmc_set_write_protection(bool enable, unsigned start_offset, unsigned size);
+
+bool drv_fmc_is_read_protection(void);
+bool drv_fmc_is_write_protection(unsigned addr);
+
+int drv_fmc_set_wdt(unsigned time_ms);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

components/system/include/drivers/chip/gpio.h

@@ -0,0 +1,60 @@
+#ifndef __GPIO_H__
+#define __GPIO_H__
+
+#include <stdbool.h>
+#include <stdint.h>
+
+#ifndef __packed
+#define __packed __attribute__((__packed__))
+#endif
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+typedef enum __packed
+{
+    _GPIO_DIR_IN,
+    _GPIO_DIR_ANALOG,
+    _GPIO_DIR_OUT,
+    _GPIO_DIR_OPEN_DRAIN,
+} gpio_dir_t;
+
+typedef enum __packed
+{
+    _GPIO_PUD_NONE,
+    _GPIO_PUD_PULL_UP,
+    _GPIO_PUD_PULL_DOWN,
+} gpio_pud_t;
+
+typedef enum __packed
+{
+    _GPIO_EXTI_EDGE_NONE,
+    _GPIO_EXTI_EDGE_FALL,
+    _GPIO_EXTI_EDGE_RISE,
+    _GPIO_EXTI_EDGE_BOTH,
+} gpio_exti_edge_t;
+
+typedef void (*gpio_exti_cb_fn)(void);
+
+void drv_gpio_enable_all(void);
+void drv_gpio_disable_all(void);
+
+int drv_gpio_pin_configure(uint8_t pin, gpio_dir_t dir, gpio_pud_t pull);
+int drv_gpio_pin_read(uint8_t pin);
+void drv_gpio_pin_write(uint8_t pin, int value);
+
+void drv_gpio_exti_callback_enable(gpio_exti_cb_fn cb);
+void drv_gpio_exti_callback_disable(void);
+
+void drv_gpio_exti_irq_enable(uint8_t pin, gpio_exti_edge_t polarity, int priority);
+void drv_gpio_exti_irq_disable(uint8_t pin);
+
+int drv_gpio_exti_get_pin(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

components/system/include/drivers/chip/i2c.h

@@ -0,0 +1,38 @@
+#ifndef __I2C_H__
+#define __I2C_H__
+
+#include "drivers/chip/_hal.h"
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+typedef void (*i2c_isr_cb_fn)(void);
+
+void drv_i2c_pin_configure_sck(hal_id_t id, uint8_t pin);
+void drv_i2c_pin_configure_sda(hal_id_t id, uint8_t pin);
+
+void drv_i2c_enable(hal_id_t id);
+void drv_i2c_disable(hal_id_t id);
+
+void drv_i2c_init(hal_id_t id, uint32_t freq);
+void drv_i2c_deinit(hal_id_t id);
+
+int drv_i2c_write(hal_id_t id, char dev_addr, const void *src, unsigned count);
+int drv_i2c_read(hal_id_t id, void *dest, char dev_addr, unsigned count);
+
+int drv_i2c_irq_callback_enable(hal_id_t id, i2c_isr_cb_fn cb);
+int drv_i2c_irq_callback_disable(hal_id_t id);
+
+void drv_i2c_irq_enable(hal_id_t id, int priority);
+void drv_i2c_irq_disable(hal_id_t id);
+
+bool drv_i2c_is_busy(hal_id_t id);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

components/system/include/drivers/chip/irq.h

@@ -0,0 +1,23 @@
+#ifndef __IRQ_H__
+#define __IRQ_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+unsigned drv_irq_disable(void);
+void drv_irq_enable(unsigned nest);
+
+unsigned drv_irq_get_nest(void);
+
+void drv_fiq_disable(void);
+void drv_fiq_enable(void);
+
+void drv_irq_hardfault_callback(void ((*cb)(void)));
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

components/system/include/drivers/chip/lpm.h

@@ -0,0 +1,19 @@
+#ifndef __LPM_H__
+#define __LPM_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+void drv_lpm_wkup_enable(unsigned id);
+void drv_lpm_wkup_disable(unsigned id);
+
+void drv_lpm_sleep(void);
+void drv_lpm_deep_sleep(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

components/system/include/drivers/chip/misc.h

@@ -0,0 +1,68 @@
+#ifndef __MISC_H__
+#define __MISC_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/**
+ * @brief 让 CPU 空转延时
+ * 
+ * @param us 微秒
+ */
+void drv_misc_busy_wait(unsigned us);
+
+/**
+ * @brief 获取变量的位带映射地址
+ *
+ * @param mem 变量地址
+ * @return 位带映射地址。如无返回 NULL
+ */
+unsigned *drv_misc_bitband(void *mem);
+
+/**
+ * @brief 读取 MCU 身份信息的 MD5 值
+ * 
+ * @param out[out] 输出
+ * @retval 0 成功
+ * @retval -1 失败
+ */
+int drv_misc_read_id_md5(unsigned char out[16]);
+
+/**
+ * @brief 设置中断向量地址
+ *
+ * @param vector 中断向量地址
+ */
+void drv_misc_set_vector(void *vector);
+
+/**
+ * @brief 获取中断向量地址
+ *
+ * @return void* 中断向量地址
+ */
+void *drv_misc_get_vector(void);
+
+/**
+ * @brief 根据具体平台，以尽可能快的速度把内存置0
+ * 
+ * @param src 内存地址
+ * @param len 内存长度
+ */
+void mem_reset(void *src, unsigned len);
+
+/**
+ * @brief 根据具体平台，以尽可能快的速度复制内存数据
+ * 
+ * @param dest[out] 目录内存
+ * @param src 源内存
+ * @param len 长度
+ */
+void mem_cpy(void *dest, const void *src, unsigned len);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

components/system/include/drivers/chip/phy.h

@@ -0,0 +1,48 @@
+#ifndef __PHY_H__
+#define __PHY_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/* Defines the PHY link speed. This is align with the speed for MAC. */
+enum phy_speed
+{
+    PHY_SPEED_10M = 0U, /* PHY 10M speed. */
+    PHY_SPEED_100M      /* PHY 100M speed. */
+};
+
+/* Defines the PHY link duplex. */
+enum phy_duplex
+{
+    PHY_HALF_DUPLEX = 0U, /* PHY half duplex. */
+    PHY_FULL_DUPLEX       /* PHY full duplex. */
+};
+
+/*! @brief Defines the PHY loopback mode. */
+enum phy_loop
+{
+    PHY_LOCAL_LOOP = 0U, /* PHY local loopback. */
+    PHY_REMOTE_LOOP      /* PHY remote loopback. */
+};
+
+typedef struct
+{
+    enum phy_speed speed;
+    enum phy_duplex duplex;
+    enum phy_loop loop;
+} phy_param_t;
+
+int drv_phy_init(unsigned phy_addr, unsigned src_clock_hz, phy_param_t *param);
+int drv_phy_read(unsigned reg, unsigned *data);
+int drv_phy_write(unsigned reg, unsigned data);
+int drv_phy_loopback(unsigned mode, unsigned speed, unsigned enable);
+int drv_phy_get_link_status(unsigned *status);
+int drv_phy_get_link_speed_duplex(unsigned *speed, unsigned *duplex);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

components/system/include/drivers/chip/spi.h

@@ -0,0 +1,74 @@
+#ifndef __SPI_H__
+#define __SPI_H__
+
+#include "drivers/chip/_hal.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+typedef enum __packed
+{
+    _SPI_MODE_0, // clock polarity is low level and phase is first edge
+    _SPI_MODE_1, // clock polarity is low level and phase is second edge
+    _SPI_MODE_2, // clock polarity is high level and phase is first edge
+    _SPI_MODE_3, // clock polarity is high level and phase is second edge
+} spi_mode_t;
+
+typedef struct
+{
+    bool ms; // false: master, true: slave
+    spi_mode_t mode;
+    bool quad_mode;
+    bool lsb_first;
+    unsigned freq;
+} spi_init_t;
+
+typedef void (*spi_isr_cb_fn)(void);
+
+void drv_spi_pin_configure_nss(hal_id_t id, uint8_t pin);
+void drv_spi_pin_configure_sck(hal_id_t id, uint8_t pin);
+void drv_spi_pin_configure_mosi(hal_id_t id, uint8_t pin);
+void drv_spi_pin_configure_miso(hal_id_t id, uint8_t pin);
+void drv_spi_pin_configure_io2(hal_id_t id, uint8_t pin);
+void drv_spi_pin_configure_io3(hal_id_t id, uint8_t pin);
+
+void drv_spi_enable(hal_id_t id);
+void drv_spi_disable(hal_id_t id);
+
+void drv_spi_init(hal_id_t id, const spi_init_t *param);
+void drv_spi_deinit(hal_id_t id);
+
+int drv_spi_poll_read(hal_id_t id, void *dest);
+int drv_spi_poll_write(hal_id_t id, uint8_t data);
+
+int drv_spi_irq_callback_enable(hal_id_t id, spi_isr_cb_fn cb);
+int drv_spi_irq_callback_disable(hal_id_t id);
+
+void drv_spi_irq_enable(hal_id_t id, bool rx, bool tx, int priority);
+void drv_spi_irq_disable(hal_id_t id, bool rx, bool tx);
+
+bool drv_spi_is_tx_ready(hal_id_t id);
+bool drv_spi_is_rx_ready(hal_id_t id);
+
+void drv_spi_dma_enable(hal_id_t id, bool tx_dma, bool rx_dma, unsigned prio_level);
+void drv_spi_dma_disable(hal_id_t id, bool tx_dma, bool rx_dma);
+
+int drv_spi_dma_irq_callback_enable(hal_id_t id, spi_isr_cb_fn cb);
+int drv_spi_dma_irq_callback_disable(hal_id_t id);
+
+void drv_spi_dma_irq_enable(hal_id_t id, int priority);
+void drv_spi_dma_irq_disable(hal_id_t id);
+
+int drv_spi_dma_set_read(hal_id_t id, void *dest, unsigned len);
+int drv_spi_dma_set_write(hal_id_t id, const void *src, unsigned len);
+void drv_spi_dma_start(hal_id_t id);
+
+bool drv_spi_dma_is_busy(hal_id_t id);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

components/system/include/drivers/chip/tick.h

@@ -0,0 +1,18 @@
+#ifndef __TICK_H__
+#define __TICK_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+void drv_tick_enable(unsigned freq);
+void drv_tick_disable(void);
+
+unsigned drv_tick_get_counter(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

components/system/include/drivers/chip/tim.h

@@ -0,0 +1,136 @@
+#ifndef __TIM_H__
+#define __TIM_H__
+
+#include "drivers/chip/_hal.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/**
+ * @param channel_id: 0..n
+ * @param channel_mask: 1 << 0, 1 << 1, ... 1 << n
+ */
+
+typedef void (*tim_isr_cb_fn)(void);
+
+/** @defgroup time base
+ * @{
+ */
+
+void drv_tim_enable(hal_id_t id);
+void drv_tim_disable(hal_id_t id);
+
+void drv_tim_init(hal_id_t id, unsigned period_ns, unsigned reload_enable);
+void drv_tim_deinit(hal_id_t id);
+
+int drv_tim_irq_callback_enable(hal_id_t id, tim_isr_cb_fn cb);
+int drv_tim_irq_callback_disable(hal_id_t id);
+
+void drv_tim_irq_enable(hal_id_t id, int priority);
+void drv_tim_irq_disable(hal_id_t id);
+
+void drv_tim_base_start(hal_id_t id);
+void drv_tim_base_stop(hal_id_t id);
+
+unsigned drv_tim_get_period_ns(hal_id_t id);
+unsigned drv_tim_get_cost_ns(hal_id_t id);
+unsigned drv_tim_get_remain_ns(hal_id_t id);
+
+/**
+ * @}
+ */
+
+/** @defgroup PWM
+ * @{
+ */
+
+void drv_pwm_pin_configure(hal_id_t id, uint8_t pin);
+
+void drv_pwm_enable(hal_id_t id);
+void drv_pwm_disable(hal_id_t id);
+
+void drv_pwm_init(hal_id_t id, unsigned period_ns, unsigned reload_enable);
+void drv_pwm_deinit(hal_id_t id);
+
+int drv_pwm_irq_callback_enable(hal_id_t id, tim_isr_cb_fn cb);
+int drv_pwm_irq_callback_disable(hal_id_t id);
+
+void drv_pwm_irq_enable(hal_id_t id, unsigned channel_mask, int priority);
+void drv_pwm_irq_disable(hal_id_t id, unsigned channel_mask);
+
+void drv_pwm_start(hal_id_t id, unsigned channel_mask, unsigned active_level, unsigned pulse_ns);
+void drv_pwm_stop(hal_id_t id, unsigned channel_mask, unsigned active_level);
+
+bool drv_pwm_is_busy(hal_id_t id);
+
+/**
+ * @}
+ */
+
+/** @defgroup one pluse
+ * @{
+ */
+
+void drv_pluse_pin_configure(hal_id_t id, uint8_t pin);
+
+void drv_pluse_enable(hal_id_t id);
+void drv_pluse_disable(hal_id_t id);
+
+void drv_pluse_init(hal_id_t id);
+void drv_pluse_deinit(hal_id_t id);
+
+int drv_pluse_irq_callback_enable(hal_id_t id, tim_isr_cb_fn cb);
+int drv_pluse_irq_callback_disable(hal_id_t id);
+
+void drv_pluse_irq_enable(hal_id_t id, unsigned channel_mask, int priority);
+void drv_pluse_irq_disable(hal_id_t id, unsigned channel_mask);
+
+void drv_pluse_set(hal_id_t id, unsigned channel_mask, unsigned active_level, unsigned period_ns, unsigned pulse_ns);
+
+bool drv_pluse_is_busy(hal_id_t id, unsigned channel);
+
+/**
+ * @}
+ */
+
+/** @defgroup input capture
+ * @{
+ */
+
+typedef enum __packed
+{
+    _IC_EDGE_RISING,
+    _IC_EDGE_FALLING,
+    _IC_EDGE_BOTH,
+} capture_edge_t;
+
+void drv_capture_pin_configure(hal_id_t id, uint8_t pin);
+
+void drv_capture_enable(hal_id_t id);
+void drv_capture_disable(hal_id_t id);
+
+void drv_capture_init(hal_id_t id, unsigned channel_mask, capture_edge_t polarity);
+void drv_capture_deinit(hal_id_t id);
+
+int drv_capture_irq_callback_enable(hal_id_t id, tim_isr_cb_fn cb);
+int drv_capture_irq_callback_disable(hal_id_t id);
+
+void drv_capture_irq_enable(hal_id_t id, unsigned channel_mask, int priority);
+void drv_capture_irq_disable(hal_id_t id, unsigned channel_mask);
+
+void drv_capture_start(hal_id_t id, unsigned channel_mask);
+void drv_capture_stop(hal_id_t id, unsigned channel_mask);
+
+unsigned drv_capture_get_cap_value(hal_id_t id, uint8_t channel_id);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

components/system/include/drivers/chip/uart.h

@@ -0,0 +1,56 @@
+#ifndef __UART_H__
+#define __UART_H__
+
+#include "drivers/chip/_hal.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+typedef struct
+{
+    uint32_t br;
+    uint8_t length;    /* 7..9 */
+    uint8_t stop_bit;  /* 1 or 2 */
+    uint8_t parity;    /* 0: none 1: even  2: odd */
+    uint8_t flow_ctrl; /* 0: none 1: RTS 2: CTS 3: RTS+CTS */
+
+} uart_param_t;
+
+typedef void (*uart_isr_cb_fn)(void);
+
+void drv_uart_pin_configure_txd(hal_id_t id, uint8_t pin);
+void drv_uart_pin_configure_rxd(hal_id_t id, uint8_t pin);
+
+void drv_uart_enable(hal_id_t id);
+void drv_uart_disable(hal_id_t id);
+
+void drv_uart_init(hal_id_t id, const uart_param_t *param);
+void drv_uart_deinit(hal_id_t id);
+
+void drv_uart_set_br(hal_id_t id, unsigned clk, unsigned baudrate);
+unsigned drv_uart_get_br(hal_id_t id, unsigned clk);
+
+int drv_uart_poll_read(hal_id_t id, void *data);
+int drv_uart_poll_write(hal_id_t id, uint8_t data);
+
+int drv_uart_fifo_read(hal_id_t id, void *data, int size);
+int drv_uart_fifo_fill(hal_id_t id, const void *data, int size);
+
+int drv_uart_irq_callback_enable(hal_id_t id, uart_isr_cb_fn cb);
+int drv_uart_irq_callback_disable(hal_id_t id);
+
+void drv_uart_irq_enable(hal_id_t id, bool rx, bool tx, int priority);
+void drv_uart_irq_disable(hal_id_t id, bool rx, bool tx);
+
+bool drv_uart_wait_tx_busy(hal_id_t id);
+
+bool drv_uart_is_tx_ready(hal_id_t id);
+bool drv_uart_is_rx_ready(hal_id_t id);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

components/system/include/drivers/chip/wdt.h

@@ -0,0 +1,32 @@
+#ifndef __WDT_H__
+#define __WDT_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+typedef enum
+{
+	_WDT_MODE_RESET,
+	_WDT_MODE_INTERRUPT_RESET
+} wdt_mode_t;
+
+void wdt_enable(void);
+void wdt_disable(void);
+
+void wdt_irq_enable(int priority);
+void wdt_irq_disable(void);
+
+void wdt_set_config(wdt_mode_t mode, int int_ms, int reset_ms);
+
+void wdt_reload(void);
+unsigned wdt_get_time_cost(void);
+
+void wdt_clear_int_flag(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif